1. Field of Invention
The invention relates to mixed signal environments, and more specifically to an interface between digital integrated circuit families for converting signals from one digital integrated circuit family to be compatible with another digital integrated circuit family.
2. Related Art
As the optical communication speed migrates to higher-data rates to meet increasing demand of network infrastructures, optical transceiver products have become a hot market attracting many companies with their various products. As a result, beyond meeting tough design requirements, two specifications have become key to differentiate one product from the other in order to gain market share: power and area consumption. Since the traditional circuit and system approaches have their own limits in terms of area and power, integrated circuit designers seek new techniques, such as replacing current mode logic (CML) with complementary metal oxide semiconductor (CMOS) logic in order to save power.
Conventionally, high-speed logic has been entirely implemented with CML circuits. However, ever decreasing feature size and decreasing power of basic electronic circuits of the CMOS logic family have made the CMOS logic family attractive to integrated circuit designers. As a result, the integrated circuit designers have been replacing high-speed logic that has been implemented using entirely CML circuits by mixing the CML family and the CMOS logic family. Mixing of the integrated circuit families in this manner typically requires an interface between the CML family and the CMOS logic family to convert signals from the CML family to be compatible with the CMOS logic family. For example, the CML family provides high-speed low-swing (a few hundred mVs) differential signals while the CMOS logic family rail-to-rail (0 to VDD) signals. In this example, an interface is required to convert the high-speed low-swing output signals of the CML family to rail-to-rail input signals for the CMOS logic family.
Conventional interfaces have utilized a two-stage amplifier, such as a differential pair and an active loaded common source amplifier, to make this conversion. The differential pair conventionally applies the low swing output signal of CML family while the active loaded common source amplifier provides rail to rail operation with further amplification. However, this conventional approach has inherently low bandwidth due to its two-pole architecture. For example, the two-pole architecture limits the speed of the conventional interface to approximately 6 or 7 GB/s when using a 40 nm CMOS fabrication technology. Additionally, performance of the conventional interface depends upon a common mode level of input. As a result, the conventional interface typically includes an additional bias circuit to provide the common mode level for its input. This additional bias circuit consumes more power and area.
Thus, there is a need for a high-speed interface between digital integrated circuit families to convert signals from one digital integrated circuit family to be compatible with another digital integrated circuit family that overcomes the shortcomings described above. Further aspects and advantages of the present invention will become apparent from the detailed description that follows.
The invention will now be described with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the reference number.